Opcodes

This table links opcodes from the SBPF bytecode ISA with their corresponding Rust implementation constant name. Each opcode also has a link to a select example from this guide where it is used, as well as its corresponding assembler mnemonic.

Opcode hex	Opcode name	Assembler mnemonic	Select example
0x07	ADD64_IMM	add64 dst, imm	Memo
0x14	SUB32_IMM	sub32 dst, imm	Fibonacci
0x15	JEQ_IMM	jeq dst, imm, off	Counter
0x17	SUB64_IMM	sub64 dst, imm	Transfer
0x18	LD_DW_IMM	lddw dst, imm	Quickstart
0x25	JGT_IMM	jgt dst, imm, off	Fibonacci
0x27	MUL64_IMM	mul64 dst, imm	Counter
0x55	JNE_IMM	jne dst, imm, off	Transfer
0x57	AND64_IMM	and64 dst, imm	Counter
0x5d	JNE_REG	jne dst, src, off	Memo
0x63	ST_W_REG	stxw [dst + off], src	Transfer
0x6a	ST_H_IMM	sth [dst + off], imm	Counter
0x71	LD_B_REG	ldxb dst, [src + off]	Fibonacci
0x72	ST_B_IMM	stb [dst + off], imm	Transfer
0x73	ST_B_REG	stxb [dst + off], src	Counter
0x79	LD_DW_REG	ldxdw dst, [src + off]	Memo
0x7a	ST_DW_IMM	stdw [dst + off], imm	Transfer
0x7b	ST_DW_REG	stxdw [dst + off], src	Transfer
0x85	CALL_IMM	call imm	Quickstart
0x95	EXIT	exit	Quickstart
0xad	JLT_REG	jlt dst, src, off	Transfer
0xb4	MOV32_IMM	mov32 dst, imm	Fibonacci
0xb7	MOV64_IMM	mov64 dst, imm	Fibonacci
0xbf	MOV64_REG	mov64 dst, src	Fibonacci